For example, the connectivity rules for metal layers can be applied and a node highlighted by selecting Metal 1 geometry. Where layout vs. schematic verification (LVS) is being performed, discrepancies between the schematic netlist and the extracted netlist are highlighted in the layout, enabling the differences to be rapidly identified and debugged. Increase in design size is inversely proportional to decrease in verification time, with larger designs showing processing speed improvements of up to 22%.

Although DRC debugging often takes more total time in the design process, LVS debugging is usually more complicated, with each individual fix taking a relatively long time. Node highlighting in L-Edit v11.1 improves design productivity significantly during LVS. For example, when the LVS indicates an open circuit between two nodes, the nodes can be highlighted to determine where they are in close proximity – the most likely point at which a connection may have been intended.

Where accidental short-circuits occur, highlighting the node incrementally helps determine where the crossover to another node occurs. The tool can also identify the shortest path between two nodes, help with visual analysis of crosstalk, and carry out certain signal integrity checks.

About Tanner EDA

Tanner EDA is a division of Tanner Research, Inc., a privately held company headquartered in Pasadena, California. Tanner EDA develops layout, verification and electronic simulation design software for analog and mixed-signal IC, MEMS and integrated optical designs on the Windows® platform. Tanner's HiPer Verify™, L-Edit Pro™ and T-Spice Pro™ tools provide a complete design flow including schematic entry, waveform probing, full-custom layout editing, placement and routing, LVS and DRC verification, netlist extraction and circuit simulation. Founded in 1988, Tanner Research, Inc. consists of three major divisions in addition to Tanner EDA.

Edtorial Contact: Bob Jones, Publitek Limited
(626) 792-3000